1. Field of the Invention
The present invention relates to an A/D converter, a solid-state image sensor using a plurality of A/D converters and a driving method of an A/D converter. More particularly, the present invention relates to an A/D converter which performs A/D conversion by comparing a ramp reference signal, which makes a predetermined change along with time, with an analog input signal, and measuring a timing at which a comparison signal indicating the comparison result changes, a solid-state image sensor using a plurality of A/D converters and a driving method of driving the A/D converters.
2. Description of the Related Art
In recent years, a solid-state image sensor, which includes, on a single chip, a plurality of pixels each including a photoelectric conversion element and a plurality of A/D converters that convert analog signals output from the pixels into digital signals, is popularly used in digital cameras and digital video cameras. A typical solid-state image sensor includes, as principal circuitry components, a plurality of pixels, a scanning circuit for addressing, and A/D converters arranged for respective columns. Especially, a MOS solid-state image sensor has a large merit upon configuring, for example, the A/D converters and scanning circuit on a single chip.
However, in consideration of such application, since characteristic variations of individual A/D converters constitute a major cause of deterioration of image quality, a proposal for reducing the characteristic variations has been made. For example, according to Japanese Patent Laid-Open No. 2005-323331, in a solid-state image sensor which mounts A/D converters on a single chip, column A/D circuits each having a voltage comparing circuit and counter are arranged in correspondence with vertical signal lines. Each voltage comparing circuit compares a pixel analog signal input via the corresponding vertical signal line for each row control line with a ramp reference signal, and generates a pulse signal having a width in the time axis direction corresponding to the magnitudes of reset and signal components. Each counter counts clocks corresponding to the width of the pulse signal until completion of comparison of the voltage comparing circuit, and holds a count value at a comparison completion timing. A communication/timing control portion controls the voltage comparing circuit to execute comparing processing of a reset component and the counter to perform a down-count operation in a first operation, and to control the voltage comparing circuit to execute comparing processing of a signal component and the counter to perform an up-count operation in a subsequent second operation. With this operation, subtraction processing of a reference component and signal component is directly performed.
In the prior art such as Japanese Patent Laid-Open No. 2005-323331, a digital signal allows subtraction processing of a reference component and signal component, and an offset of each individual A/D converter can be reduced. However, as an analog signal, the dynamic range of each A/D converter is impaired by the magnitude of a reference component.